Currently, a multi-core high performance computer is applied more widely. Moreover, as a quantity of calculating units (for example, cores) on a processor continues to increase, a memory access contention phenomenon among multiple cores further complicates a problem. In any time period of concurrent execution, memory access requests from different cores may contend for memory access to global memory resources, further triggering a conflict over resources such as a memory controller (MC), bandwidth, and a dynamic random access memory bank (for example, DRAM Bank); as a result, resource utilization is affected.
Access to a main memory is used as an example. Usually, a single transistor is used as a storage unit, N*M storage units form a storage matrix, and several storage matrices constitute a bank. Each Bank has a row-buffer; when data is to be accessed, data in a target row can be read only after the data is moved to the row-buffer. A modern DRAM system usually uses multiple Banks, and respective memory access requests are processed independently at the same time. However, if two memory access requests that are from different processes or threads access different rows of a same DRAM Bank, a conflict (or referred to as a row-buffer conflict) on the DRAM Bank may be generated, and a memory access delay is increased. A cache is used to alleviate a gap between a calculating unit and a main memory. Because the cache is closer to the calculating unit than the main memory, the cache affects calculation performance more easily. Existing processors basically use a structure of sharing a last level cache (LLC) among multiple cores. However, the LLC is also intensely contended for among multiple concurrent programs or threads. If no proper management policy is used, it is very easy to cause serious performance deterioration.
In the prior art, the LLC or the DRAM Bank is partitioned by using page coloring. Regarding page coloring-based LLC partitioning, a Cache resource is partitioned into several independent parts in a manner of performing page coloring on index bits of a cache set in a physical address, and the parts are assigned to different threads separately. Therefore, inter-thread contention due to sharing of a Cache disappears. Similar to the LLC partitioning, index bits of the DRAM Bank can also be reflected in a physical address, and the DRAM Bank can also be partitioned into several independent groups by performing coloring according to these address bits; therefore, inter-program contention on the DRAM Bank disappears. For some working sets, a relatively good performance improvement effect can be achieved.
However, when a conventional page coloring technology is used to partition a resource at a level, a negative impact is caused on utilization of a resource at another level. For example, work related to the LLC partitioning has a restriction on performance improvement of a DRAM Bank resource; similarly, work related to the DRAM Bank partitioning also affects performance of an LLC resource. In addition, because running of a modern computer system requires various working sets, an existing page coloring-based partitioning mechanism for a resource at a level is difficult to match up with features of different working sets; as a result, an optimum partitioning effect cannot be achieved, and overall performance improvement of the computer is limited.